1. Field of the Invention
This invention relates to a signal modulation system of the type for converting a plural-bit digital input signal to an encoded-bit digital output signal representative of an analog signal having a variable amplitude, and more particularly to such a signal modulation system employing the delta-sigma modulation technique.
2. Description of the Prior Art
Recently, much attention has been put on the AD (analog-digital) and DA (digital-analog) conversion technique known as the so-called .DELTA.-.SIGMA. (delta-sigma) modulation method suitable for audio measurement, etc. This technique adopts the oversampling method, and obtains a sufficiently large dynamic range in the low-frequency range (such as the frequency range about 20 KHz audible to humans) by exploiting the fact that the spectral distribution of the quantization noise is concentrated in the high-frequency range. The aforementioned .DELTA.-.SIGMA. modulation method is explained in detail in Nikkei Electronics, Aug. 8, 1988 (No. 453), pp. 216-220, and Rajio Gijutsu [Radio Technology], Sep. 1987, pp.37-44. Hence, it is not described in detail here.
That is, as shown in FIG. 20, for the .DELTA.-.SIGMA. modulator, the quantization noise generated within quantizer 30 (known as a local quantizer hereinafter) is differentiated. In this way, at the low range the quantization noise is suppressed and a small number of bits can be used to obtain the desired dynamic range. Suppose the input is X, the output is Y, and the noise of local quantizer 30 is Q, the k'th transfer characteristics of the .DELTA.-.SIGMA. modulator can be represented by the following Formula (1): EQU Y=X+(1-Z.sup.-1).sup.k .multidot.Q (1)
There are various methods of realizing the .DELTA.-.SIGMA. modulator shown in Formula (1). All of the methods with a final output represented by Formula (1) are known as .DELTA.-.SIGMA. modulators. In Formula (1), (1-Z.sup.-1).sup.k represents the differential characteristics. In addition, the local quantizer has linear quantization characteristics, and has 2.sup.m quantized values. Those 2.sup.m values can be encoded by m bits. Also, as shown in FIG. 20, the operation of local quantizer 30 is equivalent to addition of quantization noise Q to input X.sub.1. In this example, Y=X.sub.1 +Q.
Suppose the magnitude of the quantizing step width of local quantizer 30 is .DELTA., the condition is that quantization noise Q must be distributed in the range of .+-..DELTA./2. In this case, the allowable input of local quantizer 30 becomes 2.sup.m .DELTA. (P-P); input X.sub.1 of local quantizer 30 is the sum of input X and fed-back -Q.multidot.H (Z) (where P-P means "peak to peak"). Also, since the maximum value of -Q.multidot.H (Z)=-Q.multidot.(1-(1-Z.sup.-1).sup.k) is ##EQU1## the aforementioned condition is established.
If the quantization noise Q is taken as a white noise distributed in the range of .+-..DELTA./2, its power (quantization noise power) becomes .DELTA..sup.2 /12. Assuming the operation clock (sampling frequency) of the .DELTA.-.SIGMA. modulator is fs it is believed that said power is distributed uniformly over the band to fs/2 (Nyquist frequency); hence, the power density becomes .DELTA..sup.2 /12.multidot.2/fs. On the other hand, if we set the amplitude characteristic of the differential characteristic (1-Z.sup.-1).sup.k as EQU Z.sup.-1 =e.sup.-j2xf/fs, EQU we have EQU .vertline.(1-Z.sup.-1).sup.k .vertline.=2.sup.k .multidot.sin.sup.k (.pi.f/fs)
and the spectrum Nf differentiated quantization noise EQU (1-Z.sup.-1).sup.k .multidot.Q EQU becomes ##EQU2## Spectrum Nf represented by this formula is the curve shown in FIG. 21. Here, input X is assumed to be a sinusoidal wave.
An example of the specific internal structure of the aforementioned .DELTA.-.SIGMA. modulator can be explained with reference to FIG. 22.
As shown in FIG. 22, in this example, the so-called third-order 8-value .DELTA.-.SIGMA. modulator 4 is formed. That is, as shown in the figure, .DELTA.-.SIGMA. modulator 4 mainly comprises a register unit 35 which is made of 7 registers (THR1 . . . THR7) for holding threshold values; a quantizer 30 which is composed of a comparison circuit unit 20 made of seven comparators (COMP1 . . . COMP7) which compare the threshold values (THL1 . . . THL7) from register unit 35 with the input data and output the results as the prescribed flags (f1 . . . f7), respectively, an encoder unit 21 which encodes flag values (f1 . . . f7) output from comparison circuit unit 20 to the prescribed output values, and a selector unit 22 which selects one value out of the various quantized values (QL1 . . . QL8) of register unit 34 made of eight quantized values holding registers (QLR1 . . . QLR8) corresponding to said threshold values by using the flag values (f1 . . . f7) in comparison circuit unit 20; and a quantization noise differentiating filter 26 made of three delay registers R, multipliers 26a having different coefficients (1, -3, 3 in this example) and adder 26b for adding the outputs of multipliers 26a.
The operation of the aforementioned .DELTA.-.SIGMA. modulator 4 can be explained as follows. First of all, i-bit input data X (a digital signal, in this example is added to data which is delayed by unit-time delay element Z.sup.-1 by a quantization noise differentiating filter 26 and multiplied by a coefficient to become input data X.sub.1 with, say (i+3) bits. In this example, 3 bits are added without decreasing the dynamic range of said input data X.sub.1.
Input data X.sub.1, with i+3 bits becomes the input signal to the various comparators (COMP1 . . . COMP7). At comparison circuit unit 20, the input signal is compared with the various threshold levels (THL1 . . . THL7) at threshold level register unit 35. The results are represented as comparison flag values (f1 . . . f7), which are set to 0 when the threshold level is higher than the value of input X.sub.1 and which are set to 1 when the threshold level is lower than the value of input X.sub.1. Comparison flag values (f1 . . . f7) go through encoder unit 21 and become a 3-bit output Y.
In addition, comparison flag values (f1 . . . f7) are also sent to selector 22. Selector 22 reads the values of the comparison flags (f1 . . . f7) and outputs the appropriate value from quantization level register unit 34. This output data is subtracted from (i+3)-bit input data X.sub.1 to form i-bit data, which enters filter 26 for quantization noise differentiation. Each of the i-bit data then pass through unit-time delay element Z.sup.-1 at the quantization noise differentiating filter 26, and are multiplied by a coefficient. It is then added to input data X. That is, by repeating the aforementioned operations corresponding to the value of input X, the prescribed output data Y (3-bit output data in this example) can be obtained.
FIG. 23 shows a CD (compact disc) stereo system (playback system) using said .DELTA.-.SIGMA. modulator 4. This figure can be used to explain the system and its problem. A method nearly identical to the method of this example is described in Rajio Gijutsu, May 1988, pp. 140-143. Hence, explanation of the details is omitted in this case.
That is, as shown in FIG. 23, the 16-bit audio signal from CD 1 has its frequency characteristics changed at a digital equalizer 2 to form an 18-bit audio signal. Then at volume multiplier mode 8, the 18-bit data is multiplied by a 9-bit coefficient to form a 27-bit signal. The increase in the bit count from 18-bits is to prevent degradation of the output S/N (signal/noise) ratio from the input in the case when the coefficient is small, i.e., when the volume is set at a low level, which would take place if the bits added by performing multiplication were truncated. Then, oversampling is performed on the 27-bit data using an oversampling filter 3. After the sampling frequency is increased, .DELTA.-.SIGMA. modulator 4 is used to reduce the bit count to form 3-bit data. After this data is returned to an analog signal by 3-bit high-speed DAC 5, a power amplifier 6 is used to amplify the data and sound is output from speaker 7.
In said stereo system, the 16-bit audio signal from CD 1 can have its volume increased or decreased by using an external operation key to operate volume multiplier mode 8. That is, the signal output from the operation key is input to microcomputer 10 for data signal processing. Afterwards, a serial control signal is output from microcomputer 10. Then, this serial control signal is sent into volume multiplier mode 8 to perform multiplication in this configuration.
In the aforementioned stereo system, volume 8 is usually provided by a multiplier, etc.; hence, the circuit scale and calculation cycle count are large, significantly increasing the burden on both hardware and software. This is a problem.
It is an object of this invention to provide a signal modulation system which can realize a small-circuit-scale system (such as a stereo system) without a multiplier, etc., that would become a burden on hardware and software.